1
Gust Perlegos, Tsung Ching Wu: MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide. Seeq Technology, Lyon & Lyon, April 18, 1989: US04822750 (64 worldwide citation)


A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel o ...


2
William W Ip, Gust Perlegos: CMOS eprom sense amplifier. Seeq Technology, Lyon & Lyon, February 16, 1988: US04725984 (60 worldwide citation)


Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the pres ...


3
Sanjay Mehrotra, Gust Perlegos: Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array. Seeq Technology, Lyon & Lyon, September 16, 1986: US04612640 (56 worldwide citation)


An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored ...


4
Gust Perlegos, Tsung Ching Wu: MOS floating gate memory cell and process for fabricating same. Seeq Technology, Lyon & Lyon, October 20, 1987: US04701776 (55 worldwide citation)


A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel o ...


5
William W Ip, Gust Perlegos: Redundancy circuit for use in a semiconductor memory array. Seeq Technology, Lyon & Lyon, October 14, 1986: US04617651 (39 worldwide citation)


A semiconductor memory circuit having primary and redundant arrays with the capability of substituting the redundant arrays for defective primary arrays by address location.


6
Gust Perlegos, Alan L Renninger, James Yount, Maria Ryan: SONOS memory array with improved read disturb characteristic. Atmel Corporation, Schwegman Lundberg & Woessner P A, September 9, 2008: US07423912 (9 worldwide citation)


A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a c ...


7
Gust Perlegos, Alan L Renninger, James Yount, Maria Ryan: Sonos memory array with improved read disturb characteristic. Atmel Corporation, Schneck & Schneck, March 20, 2008: US20080068896-A1


A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a c ...



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