1
Ulrich Klostermann
Chanro Park, Wolfgang Raberg, Ulrich Klostermann: Memory structure and method of manufacture. Infineon Technologies, Atlis Semiconductor, Slater & Matsil L, September 9, 2008: US07423282 (5 worldwide citation)


A solid state electrolyte memory structure includes a solid state electrolyte layer, a metal layer on the solid state electrolyte layer, and an etch stop layer on the metal layer.


2
Ulrich Klostermann
Ulrich Klostermann, Chanro Park, Wolfgang Raberg: Memory having cap structure for magnetoresistive junction and method for structuring the same. Altis Semiconductor SNC, Infineone Technologies, Dicke Billig & Czaja PLLC, October 13, 2009: US07602032 (4 worldwide citation)


A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask la ...


3
Michael C Gaidis, David W Abraham, Stephen L Brown, Arunava Gupta, Chanro Park, Wolfgang Raberg: Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory. International Business Machines Corporation, Infineon Technologies, Daryl K Neff, Margaret A Pepper, May 1, 2007: US07211446 (15 worldwide citation)


A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free laye ...


4
Gregory Costrini, Frank Findeis, Gill Yong Lee, Chanro Park: Mask schemes for patterning magnetic tunnel junctions. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, February 21, 2006: US07001783 (13 worldwide citation)


Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of ...


5
Michael C Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O&apos Sullivan, Gregory Costrini, Stephen L Brown, Frank Findeis, Chanro Park: Recessed metal lines for protective enclosure in integrated circuits. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, November 2, 2004: US06812141 (13 worldwide citation)


Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the area ...


6
Ruilong Xie, Min Gyu Sung, Ryan Ryoung Han Kim, Kwan Yong Lim, Chanro Park: Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products. GLOBALFOUNDRIES, Amerson Law Firm PLLC, June 7, 2016: US09362181 (9 worldwide citation)


One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate struc ...


7
Wei Yip Loh, Kanghoon Jeon, Chanro Park: Apparatus, system, and method for tunneling MOSFETs using self-aligned heterostructure source and isolated drain. Sematech, Fulbright & Jaworski L, April 16, 2013: US08421165 (5 worldwide citation)


Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased pro ...


8
John H Zhang, Kwan Yong Lim, Steven John Bentley, Chanro Park: Self-aligned gate-first VFETs using a gate spacer recess. GLOBALFOUNDRIES, Ditthavong & Steiner P C, January 3, 2017: US09536793 (4 worldwide citation)


Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor r ...


9
Woosik Kim, Chanro Park: Method of forming dual interconnects in manufacturing MRAM cells. Infineon Technologies, Altis Semiconductor, Edell Shapiro & Finnan, June 3, 2008: US07381574 (4 worldwide citation)


A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-con ...


10
Jeremy A Wahl, Gerard M Schmid, Richard A Farrell, Chanro Park: Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process. GLOBALFOUNDRIES, Amerson Law Firm PLLC, December 9, 2014: US08906802 (3 worldwide citation)


One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with ...



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