1
Katsuyuki Musaka
Natsuki Makino, Junji Kunisawa, Keisuke Namiki, Yukio Fukunaga, Katsuyuki Musaka, Ray Fang, Emanuel Israel Cooper, John Michael Cotte, Hariklia Deligianni, Keith T Kwietniak, Brett C Baker O Neal, Matteo Flotta, Philippe Mark Vereecken: Electrolytic processing apparatus and method. Squire Sanders & Dempsey, February 15, 2007: US20070034526-A1


An electrolytic processing apparatus can planarize uniformly over an entire surface of a substrate under a low pressure without any damages to the substrate. The electrolytic processing apparatus has a substrate holder configured to hold and rotate a substrate having a metal film formed on a surface ...


2
Katsuyuki Musaka
Masayuki Kumekawa, Norio Kimura, Yukio Fukunaga, Katsuyuki Musaka, Hariklia Deligianni, Emanuel Israel Cooper, Philippe Mark Vereecken: Electrolytic processing method. Squire Sanders & Dempsey, February 15, 2007: US20070034525-A1


An electrolytic processing method is used to remove a metal film formed on a surface of a substrate. The electrolytic processing method includes providing a feeding electrode 31 and a processing electrode 32 on a table 12, providing an insulating member 36 between the feeding electrode and the proce ...


3
Panayotis Constantinou Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak, Gangadhara Swami Mathad, Sampath Purushothaman, Leathen Shi, Ho Ming Tong: Flip-Chip interconnections using lead-free solders. International Business Machines Corporation, Casey P August Esq, IBM Corporation, Ohlandt Greeley Ruggiero & Perle, May 1, 2001: US06224690 (72 worldwide citation)


An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhes ...


4
Panayotis C Andricacos, Shyng Tsong Chen, John M Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei Tsu Tseng, Philippe M Vereecken: Selective capping of copper wiring. International Business Machines Corporation, Connolly Bove Lodge & Hutz, Robert M Trepp, March 7, 2006: US07008871 (48 worldwide citation)


Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating ...


5
Panayotis Constantinou Andricacos, Hariklia Deligianni, James McKell Edwin Harper, Chao Kun Hu, Dale Jonathan Pearson, Scott Kevin Reynolds, King Ning Tu, Cyprian Emeka Uzoh: Copper alloys for chip and package interconnections. International Business Machines Corporation, Robert M Trepp, Randy W Tung, May 16, 2000: US06063506 (42 worldwide citation)


Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such ...


6
Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong Hon Wong: Method of making electroplated interconnection structures on integrated circuit chips. International Business Machines Corporation, Robert M Trepp, Connolly Bove Lodge & Hutz, March 23, 2004: US06709562 (40 worldwide citation)


A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. ...


7
Hariklia Deligianni, Robert Groves, Christopher Jahnes, Jennifer L Lund, Panayotis Andricacos, John Cotte, L Paivikki Buchwalter, David Seeger, Raul E Acosta: MEMS RF switch with low actuation voltage. IBM Corporation, Dilworth & Barrese, October 28, 2003: US06639488 (37 worldwide citation)


Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmits the RF si ...


8
Erick Gregory Walton, Dean S Chung, Lara Sandra Collins, William E Corbin Jr, Hariklia Deligianni, Daniel Charles Edelstein, James E Fluegel, Josef Warren Korejwa, Peter S Locke, Cyprian Emeka Uzoh: Electroplating apparatus and method using a compressible contact. International Business Machines Corporation, Jay H Anderson, August 7, 2001: US06270646 (35 worldwide citation)


A metal plating apparatus is described which includes a compressible member having a conductive surface covering substantially all of the surface of the substrate to be plated. The plating current is thereby transmitted over a wide area of the substrate, rather than a few localized contact points. T ...


9
Katherine L Saenger, Cyril Cabral Jr, Emanuel I Cooper, Hariklia Deligianni, Panayotis Andricacos, Philippe M Vereecken: Field effect transistor with electroplated metal gate. International Business Machines, Connolly Bove Lodge & Hutz, Robert M Trepp Esq, November 22, 2005: US06967131 (29 worldwide citation)


Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the ...


10
Katherine L Saenger, Cyril Cabral Jr, Hariklia Deligianni, Caliopi Andricacos legal representative, Philippe M Vereecken, Emanuel I Cooper: Field effect transistor with electroplated metal gate. International Business Machines Corporation, Connolly Bove Lodge & Hutz, September 26, 2006: US07112851 (27 worldwide citation)


Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the ...



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