1
Robert L Payne, Herbert Reiter: Face on face flip chip integration. VLSI Technology May 2, 2000: US06057598 (83 worldwide citation)


The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. T ...


2
John W Bloomfield, Rudi A Bischoff, Robert L Payne, Scott B Wagner, Kim Sang Gweon, Kim Tae Sik, Kim Ji Hyun, Jeong Joon Young, Yoo Chang Hyun, Dong II Shin: Mobile detection system. Samsung Electronics August 29, 1995: US05446445 (71 worldwide citation)


A mobile detection system for detecting a fire, gas leak, intruder, or other abnormal condition in a house or an office, and for alerting a central monitor, fire station, police station, or an occupant who is away from the house or office. The mobile detection system comprises a self-propelled movab ...


3
Robert L Payne: CMOS voltage comparator with internal hysteresis. Honeywell August 29, 1978: US04110641 (36 worldwide citation)


A CMOS voltage comparator with internal positive current feedback to achieve a predetermined hysteresis. The voltage level at which the switching occurs is precisely settable. Hysteresis is introduced such that when the set voltage level is exceeded, the output switches quickly and will remain in th ...


4
Robert L Payne: Initial reset signal generator and low voltage detector. Honeywell March 22, 1977: US04013902 (28 worldwide citation)


A circuit for generating an initial reset signal for a custom design CMOS digital system and for providing a diagnostic low voltage detect signal when the power supply voltage drops below a predetermined level. The circuit is fabricated with CMOS technology in conjunction with two external resistors ...


5
Robert L Payne: Hydroponics. January 19, 1982: US04310990 (26 worldwide citation)


A structure made from tubular elements which interfit to form a plural compartment hydroponic unit. The upper compartment is filled with inert root medium, houses a fluid dispensing unit, and contains slits which communicate with the lower compartment which constitutes a resevoir. The tubular housin ...


6
Robert L Payne: Bi-layer programmable resistor memory. VLSI Technology August 10, 1999: US05936880 (16 worldwide citation)


A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse typ ...


7
William K Shu, Robert L Payne: Staggered pad array. VLSI Technology March 14, 2000: US06037669 (10 worldwide citation)


A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semicondu ...


8
Stephen A Haglund, Robert L Payne: Interconnection of alarms of smoke detectors with distinguishable alarms. Honeywell August 4, 1981: US04282519 (10 worldwide citation)


A smoke detection alarm system which has at least one detector and alarm in each of the plurality of areas with an interconnection circuit whereby upon the detection of an abnormal smoke condition in any one of the areas, the annunciator or horn of the detector in the area having the abnormal condit ...


9
Robert L Payne: Cell-based integrated circuit design repair using gate array repair cells. VLSI Technology September 28, 1999: US05959905 (9 worldwide citation)


Repair cells for performing metal-only functional repairs in a cell-based circuit layout design are described. The repair cells include a gate array under layer made-up of a group of uncommitted (not interconnected) transistors. A cluster of cells can be placed within the cell-based design in variou ...


10
Robert L Payne: Scalable N-port memory structures. VLSI Technology July 13, 1999: US05923608 (8 worldwide citation)


A scalable N-port memory device using as a building block a dual-port memory device core. The dual-port memory has two ports each of which can either serve as a read or a write port. The resulting N-port memory device, besides allowing for design reuse, offers speed, density and cost advantages over ...



Click the thumbnails below to visualize the patent trend.