1
Shriram Ramanathan, Sarah E Kim, Patrick R Morrow: 3D integrated circuits using thick metal for backside connections and offset bumps. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 12, 2008: US07410884 (164 worldwide citation)


Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on t ...


2
Grant M Kloster, Michael D Goodner, Shriram Ramanathan, Patrick Morrow: Stacked device underfill and a method of fabrication. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 20, 2005: US06946384 (144 worldwide citation)


Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said s ...


3
David Staines, Grant M Kloster, Shriram Ramanathan: Method to fill the gap between coupled wafers. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 8, 2006: US07087538 (142 worldwide citation)


A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one o ...


4
Grant M Kloster, David Staintes, Shriram Ramanathan: Method of forming a stacked device filler. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 22, 2008: US07320928 (140 worldwide citation)


Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, ...


5
Mauro J Kobrinsky, Shriram Ramanathan, Scott: Wafer bonding with highly compliant plate having filler material enclosed hollow core. Intel Corporation, George Chen, December 11, 2007: US07307005 (140 worldwide citation)


The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-w ...


6
Chang Min Park, Shriram Ramanathan, Patrick Morrow, Kenneth Cadien: Portable NMR device and method for making and using the same. Intel Corporation, Darby & Darby P C, March 18, 2008: US07345479 (30 worldwide citation)


An embodiment of the invention relates to a portable or handheld device for performing NMR analysis. The device comprises a console and a strip which can be placed into the console through a slot or other means. The strip comprises a sample holding place and a microcoil for generating an excitation ...


7
Chang Min Park, Shriram Ramanathan, Patrick Morrow, Kenneth Cadien: Integrated on-chip NMR and ESR device and method for making and using the same. Intel Corporation, Darby & Darby P C, September 25, 2007: US07274191 (30 worldwide citation)


An embodiment if the invention relates to an integrated on-chip NMR or ESR device for performing chemical analysis and medical diagnostics. Specifically, the device contains, on a single substrate, a sample holding space, a magnet for generating a static magnetic field across the sample holding spac ...


8
Sriram Muthukumar, Shriram Ramanathan: Metal-metal bonding of compliant interconnect. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 6, 2010: US07750487 (28 worldwide citation)


Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.


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Shriram Ramanathan, Sarah E Kim: Method and apparatus for low temperature copper to copper bonding. Intel Corporation, Cyndi Wheeler, February 27, 2007: US07183648 (18 worldwide citation)


A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate ...



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